Memory cells of dynamic random access memories (DRAMs) generally comprise a storage capacitor and a selection transistor. An information item is stored in the storage capacitor in the form of an electrical charge, which represents a logic quantity 0 or 1. By driving the read-out or selection transistor via a word line, the information stored in the storage capacitor can be read out via a bit line. For reliable storage of the charge and distinguishability of the information read out, the storage capacitor must have a minimum capacitance. The lower limit for the capacitance of the storage capacitor is at the present time seen as approximately 25 fF.
Since the storage density increases from memory generation to memory generation, the required area of the one-transistor memory cell has to be reduced from generation to generation. At the same time, the minimum capacitance of the storage capacitor has to be maintained.
Up to the 1 Mbit generation, both the read-out transistor and the storage capacitor were realized as planar components. Starting with the 4 Mbit memory generation, a further reduction in the area of the memory cell was obtained through a three-dimensional arrangement of the storage capacitor. One possibility consists in realizing the storage capacitor in a trench. In this case, by way of example, a diffusion region adjoining the wall of the trench and also a doped polysilicon filling in the trench act as electrodes of the storage capacitor. The electrodes of the storage capacitor are thus arranged along the surface of the trench. This enlarges the effective area of the storage capacitor, on which the capacitance depends, relative to the space requirement for the storage capacitor at the surface of the substrate, which corresponds to the cross section of the trench. The packing density can be increased further by reducing the cross section of the trench whilst simultaneously increasing its depth.
Numerous measures have been implemented in the past in order to increase the storage capacitance of the trench capacitors. One measure is scaling the thickness of the storage dielectric. Furthermore, it is possible to enlarge the surface within the trench capacitor by wet-chemical expansion of the trench structure (bottle). Moreover, it is possible to enlarge the surface within the trench by means of a roughness, for example by means of HSG (hemispherical grain) polysilicon coating.
Further approaches comprise minimizing the electron depletion of the capacitor electrodes by increasing the doping of the Si electrode material, or the use of metal electrodes, as a result of which the resistance of the electrodes can at the same time be drastically reduced.
In addition, the previous NO dielectric may be replaced by high-k dielectrics in order to increase the capacitance of the trench capacitor. What is problematic for example in introducing a high-k dielectric having a high dielectric constant and also metal electrodes is, in particular, the temperature sensitivity of these materials. In addition, it is usually the case that new technologies actually have to be developed in the first place for new materials.
In order to produce trench structures having a high aspect ratio, that is to say a high ratio of depth to diameter or width, attempts are furthermore made to optimize the etching parameters for etching the hard mask stack and for etching the trench, for example by optimizing the parameters power, plasma density, frequency, bias voltage, etching gas, pressure, flow, etching time. Moreover, materials and layer thicknesses of the individual components of the hard mask for the etching of the trench are optimized. However, with the etching methods currently used to fabricate trench capacitors, technical and economic limits are increasingly being reached, since, by way of example, the etching rate and the selectivity of the etching decrease with increasing depth. As a consequence, the hard mask for the etching of the trench is etched to a great extent at the surface. At the present time, a maximum value for the aspect ratio that can be achieved by means of technologies currently being used is estimated at approximately 60 to 70.
German patent application 102 02 140, which corresponds to U.S. Patent Application Publication 2003/0136994, and U.S. Pat. No. 6,821,863, describes a method for selective epitaxial overgrowth of a cavity in a monocrystalline silicon substrate. The German and U.S. documents are incorporated herein by reference. This method can be used for example to form a trench for a trench capacitor in a silicon substrate, the trench capacitor being completed only after high-temperature steps have been carried out and being overgrown epitaxially before the high-temperature steps are carried out.